Espressif Systems /ESP32-S2 /RMT /INT_CLR

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Interpret as INT_CLR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH0_TX_END)CH0_TX_END 0 (CH0_RX_END)CH0_RX_END 0 (CH2_ERR)CH2_ERR 0 (CH0_TX_THR_EVENT)CH0_TX_THR_EVENT 0 (CH1_TX_LOOP)CH1_TX_LOOP

Description

Interrupt clear bits

Fields

CH1_TX_END

Set this bit to clear the CH1_TX_END_INT interrupt.

CH3_TX_END

Set this bit to clear the CH3_TX_END_INT interrupt.

CH2_TX_END

Set this bit to clear the CH2_TX_END_INT interrupt.

CH0_TX_END

Set this bit to clear the CH0_TX_END_INT interrupt.

CH3_RX_END

Set this bit to clear the CH3_RX_END_INT interrupt.

CH2_RX_END

Set this bit to clear the CH2_RX_END_INT interrupt.

CH1_RX_END

Set this bit to clear the CH1_RX_END_INT interrupt.

CH0_RX_END

Set this bit to clear the CH0_RX_END_INT interrupt.

CH3_ERR

Set this bit to clear the CH3_ERR_INT interrupt.

CH1_ERR

Set this bit to clear the CH1_ERR_INT interrupt.

CH0_ERR

Set this bit to clear the CH0_ERR_INT interrupt.

CH2_ERR

Set this bit to clear the CH2_ERR_INT interrupt.

CH3_TX_THR_EVENT

Set this bit to clear the CH3_TX_THR_EVENT_INT interrupt.

CH1_TX_THR_EVENT

Set this bit to clear the CH1_TX_THR_EVENT_INT interrupt.

CH2_TX_THR_EVENT

Set this bit to clear the CH2_TX_THR_EVENT_INT interrupt.

CH0_TX_THR_EVENT

Set this bit to clear the CH0_TX_THR_EVENT_INT interrupt.

CH0_TX_LOOP

Set this bit to clear the CH0_TX_LOOP_INT interrupt.

CH2_TX_LOOP

Set this bit to clear the CH2_TX_LOOP_INT interrupt.

CH3_TX_LOOP

Set this bit to clear the CH3_TX_LOOP_INT interrupt.

CH1_TX_LOOP

Set this bit to clear the CH1_TX_LOOP_INT interrupt.

Links

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